View EL4342_257369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
EL4340, EL4342
Data Sheet September 21, 2005 FN7421.1
500MHz Triple, Multiplexing Amplifiers
The EL4340 and EL4342 are fixed unity gain mux amps featuring high slew rates and excellent bandwidth for video switching. These devices feature a high impedance output state (HIZ) that enables the outputs of multiple devices to be wired together. A power-down mode (ENABLE) is included to turn off un-needed circuitry in power sensitive applications. The ENABLE pin, when pulled high, sets the EL4340 and EL4342 into standby power mode - consuming just 18mW. An added feature in the EL4340 is a latch enable function (LE) that allows independent logic control using a common logic bus.
Features
* Triple 2:1 and 4:1 multiplexers for RGB * Internally set gain-of-1 * High speed three-state outputs (HIZ) * Power-down mode (ENABLE) * Latch enable (EL4340) * 5V operation * 870 V/s slew rate * 500MHz bandwidth * Supply current 11mA/ch (EL4340) and 16mA/ch (EL4342)
Ordering Information
PART NUMBER EL4340IU EL4340IUZ (See Note) EL4340IU-T7 EL4340IUZ-T7 (See Note) EL4340IU-T13 EL4340IUZ-T13 (See Note) EL4342ILZA (See Note) EL4342ILZA-T7 (See Note) EL4342ILZA-T13 (See Note) PACKAGE 24 Ld QSOP 24 Ld QSOP (Pb-free) 24 Ld QSOP 24 Ld QSOP (Pb-free) 24 Ld QSOP 24 Ld QSOP (Pb-free) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) TAPE & REEL 7" 7" 13" 13" 7" 13" PKG. DWG. # MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0046 MDP0046 MDP0046
* Pb-free plus anneal available (RoHS compliant)
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set-top boxes * Security video * Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE EL4340 S0 0 1 X X X ENABLE 0 0 1 0 0 HIZ 0 0 X 1 0 LE 0 0 X X 1 OUTPUT INO (A, B, C) IN1 (A, B, C) Power-down High Z Last S0 State Preserved
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TABLE 2. CHANNEL SELECT LOGIC TABLE EL4342 S1 0 0 1 1 X X S0 0 1 0 1 X X ENABLE 0 0 0 0 1 0 HIZ 0 0 0 0 X 1 OUTPUT IN0 (A, B, C) IN1 (A, B, C) IN2 (A, B, C) IN3 (A, B, C) Power-down High Z
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL4340, EL4342 Pinouts
EL4340 (24 LD QSOP) TOP VIEW
32 GNDA 31 IN0A IN0A GND A IN0B NIC GND B IN0C NIC IN1A NIC 1 2 3 4 5 6 7 8 9 AV=1 AV=1 AV=1 24 NIC 23 LE 22 ENABLE 21 HIZ 20 OUTA 19 V+ 18 OUTB 17 OUTC 16 V15 NIC 14 S0 13 NIC IN1A 1 NIC 2 IN1B 3 NIC 4 IN1C 5 GNDB 6 IN2A 7 NIC 8 IN2B 9 IN2C 10 GNDC 11 IN3A 12 NIC 13 IN3B 14 NIC 15 IN3C 16 AV=1 THERMAL PAD AV=1
EL4342 (32 LD QFN) TOP VIEW
29 IN0B 27 IN0C 30 NIC 28 NIC 26 HIZ 25 ENABLE 24 NIC 23 V+ 22 OUTA 21 V20 OUTB 19 OUTC 18 S0 17 S1
IN1B 10 GND C 11 IN1C 12 LATCHED ON HIGH LE
AV=1
NIC = NO INTERNAL CONNECTION
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION
Functional Diagram EL4340
S0 EN0 DECODE DL Q C DL Q C
Functional Diagram EL4342
EN0 S0 EN1 IN0(A, B, C) IN1(A, B, C) DECODE EN2 IN2(A, B, C) IN3(A, B, C) EN3 OUT
IN0(A, B, C) IN1(A, B, C)
OUT
S1
EN1
AMPLIFIER BIAS LE HIZ ENABLE A logic high on LE will latch the last S0 state. This logic state is preserved when cycling HIZ or ENABLE functions. ENABLE HIZ AMPLIFIER BIAS
2
FN7421.1 September 21, 2005
EL4340, EL4342
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL
V+ = +5V, V- = -5V, GND = 0V, TA = 25C, Input Video = 1VP-P & RL = 500 to GND, CL = 5pF unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
IS Enabled
+IS Disabled
Enabled Supply Current (EL4340) Enabled Supply Current (EL4342) Disabled Supply Current (EL4340) Disabled Supply Current (EL4342)
No load, VIN = 0V, Enable Low
26 39
30 46 2.8 3.5 10
34 50 3.3 4 100
mA mA mA mA A V mA
No load, VIN = 0V, Enable High No load, VIN = 0V, Enable High No load, VIN = 0V, Enable High VIN = 3.5V, RL = 500 RL = 10 to GND
2.3 3
-IS Disabled VOUT IOUT VOS VOS Ib ROUT ROUT RIN ACL or AV ITRI LOGIC VIH VIL IIH IIL AC GENERAL tS
Disabled Supply Current Positive and Negative Output Swing Output Current Output Offset Voltage (EL4340) Output Offset Voltage (EL4342) Input Bias Current HIZ Output Resistance Enabled Output Resistance Input Resistance Voltage Gain Output Current in Three-state
3.1 80
-15 -10
3.4 135
7 +15 +10 -2 1.4 0.2 10 -3
mV mV A M M
VIN = 0V HIZ = Logic High HIZ = Logic Low VIN = 3.5V VIN = 1.5V, RL= 500 VOUT = 0V
-1
0.98 8
0.99 15
1.02 22
V/V A
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V
2 0.8 235 270 2 320 3
V V A A
0.1% Settling Time
Step = 1V DC, PSRR V+ & V- combined DC, PSRR V+ & V- combined f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.5pF 52 52
10 72 56 75
ns dB dB dB
PSRR (EL4340) Power Supply Rejection Ratio PSRR (EL4342) Power Supply Rejection Ratio ISO Channel Isolation
3
FN7421.1 September 21, 2005
EL4340, EL4342
Electrical Specifications
PARAMETER dG dP BW FBW V+ = +5V, V- = -5V, GND = 0V, TA = 25C, Input Video = 1VP-P & RL = 500 to GND, CL = 5pF unless otherwise specified. (Continued) DESCRIPTION Differential Gain Error Differential Phase Error -3dB Bandwidth 0.1dB Bandwidth 0.1dB Bandwidth SR Slew Rate CONDITIONS NTC-7, RL = 150, CL = 1.5pF NTC-7, RL = 150, CL = 1.5pF CL = 1.5pF CL = 1.5pF CL = 4.7pF 25% to 75%, RL = 150, Input Enabled, CL = 1.5pF MIN TYP 0.02 0.02 500 60 120 MAX UNIT % MHz MHz MHz V/s
870
SWITCHING CHARACTERISTICS VGLITCH EL4340 VGLITCH EL4342 tSW-L-H tSW-H-L tr, tf tpd tLH Channel -to-Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch Channel -to-Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch Channel Switching Time Low to High Channel Switching Time High to Low Rise & Fall Time Propagation Delay Latch Enable Hold time (EL4340 only) VIN = 0V, CL = 1.5pF VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 90% 10% to 10% LE = 0 40 300 200 20 200 200 18 20 1.1 0.9 10 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P ns ns ns ns ns
Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1 10 FREQUENCY (MHz) 100 1K CL INCLUDES 1.5pF BOARD CAPACITANCE CL=4.7pF CL=2.2pF CL=1.5pF SOURCE POWER=-20dBm CL=16.5pF NORMALIZED GAIN (dB) CL=11.5pF CL=7.3pF CL=6.2pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 1 10 100 1K FREQUENCY (MHz) RL=100 RL=150 RL=500 RL=1k SOURCE POWER=-20dBm
FIGURE 1. GAIN vs FREQUENCY vs CL
FIGURE 2. GAIN vs FREQUENCY vs RL
4
FN7421.1 September 21, 2005
EL4340, EL4342 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
0.2 SOURCE 0.1 POWER=-20dBm 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1 10 100 FREQUENCY (MHz) 1K 0.1 0.1 1 10 FREQUENCY (MHz) 100 1K CL=1.5pF CL=4.7pF OUTPUT RESISTANCE () 10 100
(Continued)
1
FIGURE 3. 0.1dB GAIN vs FREQUENCY
FIGURE 4. ROUT vs FREQUENCY
0.8 0.6 OUTPUT VOLTAGE (V) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 TIME (5ns/DIV) RL=500 CL=1.5pF OUTPUT VOLTAGE (V)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 TIME (5ns/DIV) RL=500 CL=1.5pF
FIGURE 5. EL4340 TRANSIENT RESPONSE
FIGURE 6. EL4342 TRANSIENT RESPONSE
0 -10 -20 -30 -40 (dB) -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1K OFF ISOLATION INPUT X TO OUTPUT X (dB) INPUT X TO OUTPUT Y CROSSTALK
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1K OFF ISOLATION INPUT X TO OUTPUT X INPUT X TO OUTPUT Y CROSSTALK
FIGURE 7. EL4340 CROSSTALK AND OFF ISOLATION
FIGURE 8. EL4342 CROSSTALK AND OFF ISOLATION
5
FN7421.1 September 21, 2005
EL4340, EL4342 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
20 10 0 -10 PSRR (dB) PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.3 1 10 FREQUENCY (MHz) 100 1K PSRR (V-) PSRR (V+) 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0.3 1 10 FREQUENCY (MHz) 100 1K PSRR (V-) PSRR (V+)
(Continued)
FIGURE 9. EL4340 PSRR CHANNELS A, B, C
FIGURE 10. EL4342 PSRR CHANNELS A, B, C
1V/DIV
1V/DIV
S0, S1 50 TERM.
VIN = 0V
S0, S1 50 TERM.
VIN = 1V
0 20mV/DIV 0.5V/DIV
0
0 VOUT A, B, C 20ns/DIV
0
VOUT A, B, C 20ns/DIV
FIGURE 11. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FIGURE 12. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
ENABLE 50 TERM. 1V/DIV
VIN = 1V
0 100mV/DIV VOUT A, B, C 0 20ns/DIV
0
1V/DIV
0
VOUT A, B, C 20ns/DIV
FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V
6
FN7421.1 September 21, 2005
EL4340, EL4342 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
HIZ 50 TERM. 1V/DIV VIN = 0V HIZ 50 TERM. 1V/DIV
(Continued)
VIN=1V
0 200mv/DIV
0
0 VOUT A, B, C 10ns/DIV
1V/DIV
VOUT A, B, C 0 10ns/DIV
FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V
60 VOLTAGE NOISE (nV/Hz) 50 40 30 20 10 0 100
3 POWER DISSIPATION (W) 2.5 2 1.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.857W QFN32 JA=35C/W
1.136W 1 0.5 0 QSOP24 JA=88C/W
1K
10K
100K
0
25
50
75 85 100
125
150
FREQUENCY (Hz)
AMBIENT TEMPERATURE (C)
FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
1.2 POWER DISSIPATION (W) 1 0.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
870mW QSOP24 JA=115C/W
758mW 0.6 0.4 0.2 0
QFN32 JA=125C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
7
FN7421.1 September 21, 2005
EL4340, EL4342
IEL4342 (32 LD QFN) 1 EL4340 (24 LD QFN) 8 PIN NAME IN1A NIC IN1B IN1C GNDB IN2A IN2B IN2C GNDC IN3A IN3B IN3C S1 S0 OUTC OUTB VOUTA V+ ENABLE Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 3 Circuit 3 Circuit 4 Circuit 3 Circuit 4 Circuit 2 EQUIVALENT CIRCUIT Circuit 1
DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. Channel 1 input for output amplifier "B" Channel 1 input for output amplifier "C" Ground pin for output amplifier "B" Channel 2 input for output amplifier "A" Channel 2 input for output amplifier "B" Channel 2 input for output amplifier "C" Ground pin for output amplifier "C" Channel 3 input for output amplifier "A" Channel 3 input for output amplifier "B" Channel 3 input for output amplifier "C" Channel selection pin MSB (binary logic code) Channel selection pin. LSB (binary logic code) Output of amplifier "C" Output of amplifier "B" Negative power supply Output of amplifier "A" Positive power supply Device enable (active low). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic High on this pin puts device into powerdown mode. In power-down mode only logic circuitry is active. All logic states are preserved post power-down. This state is not recommended for logic control where more than one MUX-amp share the same video output line. Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic state. HIZ and ENABLE functions are not latched with the LE pin. Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. Channel 0 for output amplifier "C" Channel 0 for output amplifier "B" Channel 0 for output amplifier "A" Ground pin for output amplifier "A"
V+ V+ OUT VCIRCUIT 3
2, 4, 8, 13, 15, 4, 7, 9, 13, 15, 24, 28, 30 24 3 5 6 7 9 10 11 12 14 16 17 18 19 20 21 22 23 25 10 12 5 NA NA NA 11 NA NA NA NA 14 17 18 16 20 19 22
23 26 21
LE HIZ
Circuit 2 Circuit 2
27 29 31 32
6 3 1 2
IN0C IN0B IN0A GNDA
V+
Circuit 1 Circuit 1 Circuit 1 Circuit 4
IN
LOGIC PIN
21K 33K
+ 1.2V -
GND V-
V-
CIRCUIT 1
CIRCUIT 2
V+ GNDA GNDB GNDC VCIRCUIT 4
CAPACITIVELY COUPLED ESD CLAMP
THERMAL HEAT SINK PAD V-
~1M
SUBSTRATE
8
FN7421.1 September 21, 2005
EL4340, EL4342 AC Test Circuits
EL4340 & EL4342 VIN 50 or 75 CL 5pF RL 500
split between the PCB capacitance and an external load capacitor.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane.
Control Signals
S0, S1, ENABLE, LE, HIZ - These are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE, LE, HIZ pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. For control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output.
FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
TEST EQUIPMENT 50 or 75 50 or 75
EL4340 & EL4342 VIN 50 or 75 CL 5pF RS 475
FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50 OR 75 INPUT TERMINATED EQUIPMENT
EL4340 & EL4342 VIN 50 or 75 CL 5pF RS 50 or 75 TEST EQUIPMENT 50 or 75
Power-up Considerations
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 21) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+
FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED. FIGURE 20. TEST CIRCUITS
Figure 20A illustrates the optimum output load for testing AC performance. Figure 20B illustrates the optimun output load when connecting to 50 input terminated equipment.
Application Information
General
The EL4340 and EL4342 triple 2:1 and 4:1 MUX amps are ideal as the matrix element of high performance switchers and routers. Key features include buffered high impedance analog inputs and excellent AC performance at output loads down to 150 for video cable-driving. The unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500. Total output capacitance can be
V+ SUPPLY LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY SCHOTTKY PROTECTION S0 GND IN0 IN1 VVVV+ VV+ V+
V+ LOGIC CONTROL V+ OUT V-
EXTERNAL CIRCUITS
FIGURE 21. SCHOTTKY PROTECTION CIRCUIT
9
FN7421.1 September 21, 2005
EL4340, EL4342
HIZ State
An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 15ns (Figure 16) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M with approximately 1.5pF in parallel with a 10A bias current from the output. Use this state when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is same as the active state. sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible - Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
ENABLE and Power-down States
The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power-down state is established within approximately 80ns (Figure 14), if a logic high (>2V) is placed on the ENABLE pin. In the Power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Do not use this state as a high impedance output when several MUX amps share the same output line.
LE State
The EL4340 is equipped with a Latch Enable pin. A logic high (>2V) on the LE pin latches the last logic state. This logic state is preserved when cycling HIZ or ENABLE functions.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and V-. The EL4342 uses the package with pad dimensions of D2 = 2.48mm and E2 = 3.4mm. Maximum AC performance is achieved if the thermal pad is attached to a dedicated de-coupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1" x 1" pad area is sufficient for the EL4342 that is dissipating 0.5W in +50C ambient. Pad area requirements should be evaluated on a case by case basis.
Application Example
Figure 22 illustrates the use of the EL4342, two ISL84517 SPST switches and one NC7ST00P5X NAND gate to mux 3 different component video signals and one RGB video signal. The SPDT switches provide the sync signal for the RGB video and disconnects the sync signal for the component signal.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid
10
FN7421.1 September 21, 2005
5V OPTIONAL SCHOTTKY PROTECTION Y1 Y2 Y3 R
0.1F
0.1F
-5V
31 1 7 12
INOA IN1A IN2A IN3A
EL4342IL
V+ VOUTA OUTB
23 21 22 20 19 32 6 11 2 4 8 13 15 24
1nF
1nF
Pb1 Pb2 Pb3 G
29 3 9 14
INOB IN1B IN2B IN3B
OUTC GNDA GNDB GNDC NIC NIC NIC NIC NIC NIC NIC NIC HIZ
11
FN7421.1 September 21, 2005
R16 500 R17 500
R18 500
Pr1 Pr2 Pr3 B
27 5 10 16
INOC IN1C IN2C IN3C
EL4340, EL4342
28 30 26
R1 75
R2 75
R3 75 R4 75
R5 75 R6 75
R7 75 R8 75
R9 75 R10 75
R11 75 R12 75 QFN
ENABLE 25 S0 18 S1 17
5V
0.1F
0.1F
-5V
H SYNC
1 -5V
ISL84517IH-T
COM SOT-23 IN 4 V+ V-
5 3
1nF
1nF
5V
0.1F
0.1F
NC 2 5V 0.1F
V SYNC
ISL84517IH-T
1 COM SOT-23 IN 4 V+ V-
5 3
1nF
1nF
NC7ST00P5X
5V 5 INPUT 1 4 OUT 3 GND INPUT 2 SC70 LOGIC INPUTS 1nF
NC 2
FIGURE 22. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL
EL4340, EL4342 QSOP Package Outline Drawing
(R)
12
FN7421.1 September 21, 2005
EL4340, EL4342 QFN Package Outline Drawing
NOTE: The package drawings shown here may not be the latest versions. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7421.1 September 21, 2005

▲Up To Search▲

Price & Availability of EL4342

	To Download EL4342 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .